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Core Interfaces
5
PCI Bus Signals
Table 5-1 lists the signals used in the PCI interface. The "Used On" column indicates which core configurations use
each signal. For example, REQN is only used on PCI Master cores (M), IDSEL is only used on PCI Target cores (T),
and PAR64 is only used on 64-bit cores. Note that the "Type" column describes the characteristics of the signal in the
PCI specification, not necessarily its usage in a particular core. For example, TRDYN is bidirectional for PCI Target/
Master cores but only an input to PCI Target cores.
Table 5-1 · PCI Bus Interface Signals
Name
PCICLK
PCIRSTN
IDSEL
AD
Type
Bidirectional
Input
Input
Bidirectional
Used
On
All
All
T
All
Description
33 MHz or 66 MHz clock input or output for the PCI core
Active low asynchronous reset
Active high Target select used during configuration read and write transactions
Multiplexed 32-bit or 64-bit address and data bus. Valid address is indicated by FRAMEN
assertion.
Bus command and byte enable information. During the address phase, the lower four bits
CBEN
Bidirectional
All
define the bus command. During the data phase, they define the byte enables (active high).
This bus is 4 bits wide in 32-bit PCI systems and 8 bits wide in 64-bit systems.
PAR
FRAMEN
Bidirectional
Bidirectional (STS)
All
All
Parity signal. Parity is even across AD[31:0] and CBE[3:0].
Active low signal indicating the beginning and duration of an access. While FRAMEN is
asserted, data transfers continue.
DEVSELN Bidirectional (STS)
All
Active low output from the Target indicating that it is the Target of the current access
IRDYN
TRDYN
STOPN
PERRN
SERRN
REQN
GNTN
INTAN
INTBN
INTCN
INTDN
PAR64
REQ64N
Bidirectional (STS)
Bidirectional (STS)
Bidirectional (STS)
Bidirectional (STS)
Bidirectional (OD)
Output
Input
Bidirectional
Input
Input
Input
Bidirectional
Bidirectional (STS)
All
All
All
All
T
M
M
TAll
All
All
All
64
64
Active low signal indicating that the bus Master is ready to complete the current dataphase
transaction
Active low signal indicating that the Target is ready to complete the current dataphase
transaction
Active low signal from the Target requesting termination of the current transaction
Active low parity error signal
Active low system error signal. This signal reports PCI address parity errors.
Active low output used by the PCI Master controller to request bus ownership
Active low input from the system arbiter indicating that the core may claim bus ownership
Active low interrupt input and request
Active low input interrupt
Active low input interrupt
Active low input interrupt
Upper parity signal. Parity is even across AD[63:32] and CBE[7:4]. This signal is not
required for 32-bit PCI systems.
Active low signal with the same timing as FRAMEN indicating that the Master requests a
data transfer over the full 64-bit bus. This signal is not required for 32-bit PCI systems.
Note:
Active low signals are designated with a trailing uppercase N .
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